-- -- nikuvdp.vhd -- -- Copyright (C)2000,2001 Kunihiko Ohnaka -- All rights reserved. -- -- $Id: nikuvdp.vhd,v 1.2 2001/09/18 15:35:50 kuni Exp $ -- library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; entity nikuvdp is port( -- Video Engine Clock (21.477MHz) pVideoClk : in std_logic; -- MSX Slot Signals pSltClk : IN std_logic; pSltRst_n : IN std_logic; pSltSltsl_n : IN std_logic; pSltIorq_n : IN std_logic; pSltRd_n : IN std_logic; pSltWr_n : IN std_logic; pSltAdr : IN std_logic_vector(15 downto 0); pSltDat : INOUT std_logic_vector(7 downto 0); pSltBdir_n : OUT std_logic; pSltCs1 : IN std_logic; pSltCs2 : IN std_logic; pSltCs12 : IN std_logic; pSltRfsh_n : IN std_logic; pSltWait_n : IN std_logic; pSltInt_n : INOUT std_logic; pSltM1_n : IN std_logic; pSltMerq_n : IN std_logic; -- pSltClk2 : IN std_logic; -- pSltRsv5 : OUT std_logic; -- pSltRsv516 : OUT std_logic; -- Graphic Piece Controller (GPC) signals. pRamAddr : OUT std_logic_vector(18 downto 0); pRamCeX_n : OUT std_logic; pRamOeX_n : OUT std_logic; pRamWeX_n : OUT std_logic; pRamDataX : INOUT std_logic_vector(7 downto 0); pRamCeY_n : OUT std_logic; pRamOeY_n : OUT std_logic; pRamWeY_n : OUT std_logic; pRamDataY : INOUT std_logic_vector(7 downto 0); -- Video Output -- Video DAC(MB40988) clock pVDACClk : OUT std_logic; -- 18bit digital color output pVideoR : OUT std_logic_vector( 5 downto 0); pVideoG : OUT std_logic_vector( 5 downto 0); pVideoB : OUT std_logic_vector( 5 downto 0); -- Sync Signals pVideoHS_n : OUT std_logic; pVideoVS_n : OUT std_logic; pVideoCS_n : OUT std_logic; -- CXA1645(RGB->NTSC Encoder) clock and signal. pVideoSC : OUT std_logic; pVideoSYNC : OUT std_logic; -- test pins pTest0 : OUT std_logic; pTest1 : OUT std_logic ); end nikuvdp; architecture RTL of nikuvdp is -- constant PORT_BASE_ADDR : std_logic_vector( 5 downto 0) := "100110"; -- 0x98 constant PORT_BASE_ADDR : std_logic_vector( 1 downto 0) := "00"; -- 0x00-3f component GPC port( pVideoClk : in std_logic; pCpuClk : in std_logic; pCpuReset_n : in std_logic; pCpuIrq_n : out std_logic; pCpuAddr : in std_logic_vector( 7 downto 0); pCpuData_in : in std_logic_vector( 7 downto 0); pCpuData_out : out std_logic_vector( 7 downto 0); pCpuWait_n : out std_logic; plsCpuWr : in std_logic; plsCpuRd : in std_logic; pRamAddr : OUT std_logic_vector(18 downto 0); pRamCeX_n : OUT std_logic; pRamOeX_n : OUT std_logic; pRamWeX_n : OUT std_logic; pRamDataX : INOUT std_logic_vector(7 downto 0); pRamCeY_n : OUT std_logic; pRamOeY_n : OUT std_logic; pRamWeY_n : OUT std_logic; pRamDataY : INOUT std_logic_vector(7 downto 0); pVDACClk : OUT std_logic; pVideoR : OUT std_logic_vector( 5 downto 0); pVideoG : OUT std_logic_vector( 5 downto 0); pVideoB : OUT std_logic_vector( 5 downto 0); pVideoHS_n : OUT std_logic; pVideoVS_n : OUT std_logic; pVideoCS_n : OUT std_logic; pVideoSC : OUT std_logic; pVideoSYNC : OUT std_logic; pTest0 : OUT std_logic; pTest1 : OUT std_logic ); end component; signal gpcPlsCpuWr : std_logic; signal gpcPlsCpuRd : std_logic; signal dCpuWr_n : std_logic; signal ddCpuWr_n : std_logic; signal dCpuRd_n : std_logic; signal ddCpuRd_n : std_logic; signal Addr_in : std_logic_vector( 7 downto 0); signal Data_in : std_logic_vector( 7 downto 0); signal gpcData_out : std_logic_vector( 7 downto 0); signal gpcWait_n : std_logic; signal cpuWr_n : std_logic; signal cpuRd_n : std_logic; signal pCpuData : std_logic_vector( 7 downto 0); signal pCpuCs0_n : std_logic; begin -- pSltRsv5 <= '1'; -- pSltRsv16 <= '1'; ------------------------------------------------------------------------------- -- MSX Slot 3-state control ------------------------------------------------------------------------------- pSltBdir_n <= '0' when (pSltSltsl_n = '0' and pSltRd_n = '0') or (pSltIorq_n = '0' and pSltRd_n = '0' and pSltAdr(7 downto 6) = PORT_BASE_ADDR) else '1'; pSltDat <= gpcData_out when pSltIorq_n = '0' and pSltRd_n = '0' and pSltAdr(7 downto 6) = PORT_BASE_ADDR else (others => 'Z'); pCpuCs0_n <= pSltIorq_n; -- falling edge gpcPlsCpuWr <= '1' when ( dCpuWr_n = '1' and cpuWr_n = '0' ) and (pSltAdr(7 downto 6) = PORT_BASE_ADDR) else '0'; -- falling edge gpcPlsCpuRd <= '1' when ( dCpuRd_n = '1' and cpurd_n = '0' ) and (pSltAdr(7 downto 6) = PORT_BASE_ADDR) else '0'; cpuWr_n <= pSltWr_n or pCpuCs0_n; cpuRd_n <= pSltRd_n or pCpuCs0_n; Data_in <= pSltDat; Addr_in <= pSltAdr(7 downto 0); process( pSltClk, pSltRst_n ) begin if (pSltRst_n = '0') then dCpuWr_n <= '1'; dCpuRd_n <= '1'; ddCpuWr_n <= '1'; ddCpuRd_n <= '1'; elsif (pSltClk'event and pSltClk = '1') then dCpuWr_n <= cpuWr_n; ddCpuWr_n <= dCpuWr_n; dCpuRd_n <= cpuRd_n; ddCpuRd_n <= dCpuRd_n; end if; end process; ------------------------------------------------------------------------------- -- Connect Components ------------------------------------------------------------------------------- graphic : GPC port map( pVideoClk, pSltClk, pSltRst_n, pSltInt_n, Addr_in, Data_in, gpcData_out, gpcWait_n, gpcPlsCpuWr, gpcPlsCpuRd, pRamAddr, pRamCeX_n,pRamOeX_n,pRamWeX_n,pRamDataX, pRamCeY_n,pRamOeY_n,pRamWeY_n,pRamDataY, pVDACClk, pVideoR, pVideoG,pVideoB, pVideoHS_n,pVideoVS_n,pVideoCS_n, pVideoSC, pVideoSYNC, pTest0, pTest1 ); end RTL;